1. Field of the Invention
This invention generally relates to computer-implemented methods, carrier media, and systems for creating a defect sample for use in selecting one or more parameters of an inspection recipe. Certain embodiments relate to a computer-implemented method for creating a defect sample that has one or more characteristics that are substantially the same as one or more characteristics of all the defects detected on a wafer.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on a specimen such as a reticle and a wafer. Inspection processes have always been an important part of fabricating semiconductor devices such as integrated circuits. However, as the dimensions of semiconductor devices decrease, inspection processes become even more important to the successful manufacture of acceptable semiconductor devices. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices. Accordingly, much work in the inspection field has been devoted to designing inspection systems that can detect defects having sizes that were previously negligible.
Many different types of inspection systems have adjustable output acquisition and sensitivity (or defect detection) parameters such that different parameters can be used to detect different defects or avoid sources of unwanted (nuisance) events. Although an inspection system that has adjustable output acquisition and sensitivity parameters presents significant advantages to a semiconductor device manufacturer, these inspection systems are essentially useless if the incorrect output acquisition (e.g., data, signal, and/or image acquisition) and sensitivity parameters are used for an inspection process. For example, incorrect or non-optimized output acquisition parameters may produce such high levels of noise that no defects can be detected in the generated output. In addition, since the defects, process conditions, and noise on a specimen such as a reticle and a wafer may vary dramatically (and since the characteristics of the specimen itself may vary dramatically), the best output acquisition and sensitivity parameters for detecting the defects on a particular specimen may be difficult, if not impossible, to predict. Therefore, although using the correct output acquisition and sensitivity parameters will have a dramatic effect on the results of inspection, it is conceivable that many inspection processes are currently being performed with incorrect or non-optimized output acquisition and sensitivity parameters.
An optimal inspection recipe for a semiconductor layer should detect as many defects of interest (DOI) as possible while maintaining a substantially low nuisance rate. Optimizing an inspection recipe generally involves tuning the parameters used in the recipe until the optimal result is achieved. The set of parameters to be tuned thus depends on the detection algorithm used. In the case of bright field (BF) inspection systems commercially available from KLA-Tencor, San Jose, Calif., the detection algorithms may be either auto-thresholding (AT), segmented auto-thresholding (SAT) or multiple die auto-thresholding (MDAT), and the inspection parameters are segment breaks and thresholds. In the case of dark field (DF) inspection systems commercially available from KLA-Tencor, the detection algorithms may be FAST and HLAT algorithms.
One best known method for recipe optimization is to run a substantially “hot” inspection thereby increasing the likelihood of detecting DOI but at the expense of substantially high nuisance rate. The user then takes this hot lot and the wafer to a scanning electron microscope (SEM) for review. The user reviews the defects using the SEM and classifies the defects as real, nuisance, or DOI. Once enough of each type of defect is classified, the user attempts to set the correct segmentation breaks and threshold values in order to create a recipe that will detect enough of the DOI and have as few as possible of the nuisance defects detected. The more defects that are classified, the better the recipe can be. The user may then re-inspect the wafer using the new recipe and use the SEM to review the defects detected on the wafer using the new recipe. In this manner, the re-inspection and defect review may be performed in an iterative manner until the user determines that satisfactory defect detection can be achieved by the recipe based on defect review results.
One problem with such methods is that it takes significant time to SEM review a single defect. In addition, the need for multiple trips between the inspection system and the SEM adds significant time to the recipe setup. The user would ideally like to review the smallest number of defects possible that would still produce an accurate recipe and be able to do this in one trip to the SEM. However, because of the nature of the distribution of defects in a hot lot, any kind of sampling, including random sampling, that does not take into account the distribution of defects would produce a sampled lot that would be overly weighted towards the nuisance defects, and in most cases, it would not produce a classified lot that was useable for setting segment breakpoints or detection threshold values.
There are many sampling methods used in various technical fields. For semiconductor defect review, the most common method is random sampling of defects based on some selected attributes, e.g., defect size, defect density, or defect clusters. Those methods are designed for statistical process control (SPC). There are some sophisticated methods created for special purposes such as diversity sampling designed for the discovery of defect types. Examples of methods that can be performed for such purposes are described in commonly owned U.S. patent application Ser. No. 11/146,342 by Dishner et al. filed Jun. 6, 2005, which published as U.S. Patent Application Publication No. 2006/0287751 on Dec. 21, 2006, and which is incorporated by reference as if fully set forth herein.
While such sampling methods may be useful for their designed purposes, they are not suitable for recipe optimization. In particular, those sampling methods do not consider the distribution of defects in the space of detection parameters. Furthermore, such methods completely break down when dealing with extremely hot inspection results in which the vast majority of the defects are nuisances. In particular, the randomness of the currently used sampling methods will pick mostly nuisance defects.
Accordingly, it would be advantageous to develop computer-implemented methods, carrier media, and/or systems for efficient sampling of defects for recipe optimization that take into account the distribution of the defects in a typical hot lot to produce a sampled lot that can be taken to a SEM and used to produce a valid set of segment breakpoints and detection thresholds, in a single trip to the SEM.